my 1st verilog project ^^

every semester there must have (big)mini project that we need to do in week 14(last week of semester) as computer engineering student since Y1S1...-.- this sem we use Modelsim (year 1 use Multisim). In this project, there are a few people in a group to do several different block. The block I do was BCD counter...from FSM diagram to coding until see the correct waveform...really can kill us - but finally we can fixed it and very happy to see the result^^.


verilog coding


get the output^^


RTL modeling^^~


top level modeling ^^~~

"duno what miniproject for next sem le?"