The End for y2s1

Today is the last paper for me to end my year Two semester One after struggle for so long with course work and test (and also stay in kampar for 4 months long lo -.- ~ home sick). yeah finaly... (^^):" happy holidays".






"peace ^.<"

raining season

long time already there was no rain in kampar, starting this week monday, our Rain God start to give us heavy rain every day around 4:30 pm. There still raining at 6 o'clock (dinner time), we can't cycle to eat, therefore we can only walk with our umbrella...walk with umbrella in a heavy raining day, just to out for dinner... (i think in kampar, only we did that -.- lol''').









"Today, i think we will repeat to do it again"

Boring day + CWm = @.T

today quite boring..lo...still got six day for another exam. my boring mood become another mood (no mood liao) when check the release of BMP mid term marks...



my result was half-half but because there was 2 mid term(y got 2 midterm~) ..then after convert by divide with 200 and x 20% = nothing liao..(dissapointed)......zzzz . Luckily the result was release after the final exam for BMP, else it will disturb my final exam^^ mood.

"wait for another 30% BMP course work marks"

Raya 2009

yesterday just finish my second paper for this semester- basic microprocessor,
after this subject I going to have my next paper only after raya. So, I can celebrate Raya lo...^^but..when I check back my time table, there are 3 subject come continuous after Raya...




therefore, this year raya I going to celebrate it with study-ing... -.- ~ z



"selamat hari raya"

my 1st verilog project ^^

every semester there must have (big)mini project that we need to do in week 14(last week of semester) as computer engineering student since Y1S1...-.- this sem we use Modelsim (year 1 use Multisim). In this project, there are a few people in a group to do several different block. The block I do was BCD counter...from FSM diagram to coding until see the correct waveform...really can kill us - but finally we can fixed it and very happy to see the result^^.


verilog coding


get the output^^


RTL modeling^^~


top level modeling ^^~~

"duno what miniproject for next sem le?"